This invention relates to a frequency synthesizer with a phase-locked loop (PLL). Such a frequency synthesizer is called a PLL frequency synthesizer.
As well known in the art, the PLL frequency synthesizer comprises a reference signal generator, a voltage controlled oscillator, a variable frequency divider, a phase-frequency comparator, and a control voltage supplying circuit. The reference signal generator generates a reference signal with a reference frequency. Responsive to a control voltage signal, the voltage controlled oscillator generates a voltage controlled signal having a controllable oscillating frequency. The PLL frequency synthesizer produces the voltage controlled signal as an output signal. Therefore, the output signal has an output frequency equal to the controllable oscillating frequency. The output signal is supplied to the variable frequency divider. The variable frequency divider is also supplied with a designated dividing number D which defines the output frequency, where D represents a positive integer. The variable frequency divider frequency divides the output signal on the basis of the designated dividing number D to produce a divided signal. In other words, the variable frequency divider is for frequency dividing the output signal by a factor 1/D. The phase-frequency comparator is supplied with the reference signal and the divided signal. The phase-frequency comparator detects a phase-frequency difference between the reference signal and the divided signal to produce a phase-frequency difference signal indicative of the phase-frequency difference. In other words, the phase-frequency difference signal indicates one of lag and lead phases which the divided signal has in comparison with the reference signal. Responsive to the phase-frequency difference signal, the control voltage supplying circuit supplies the control voltage signal to the voltage controlled oscillator.
More specifically, the control voltage supplying circuit comprises a current flow control circuit and a loop filter. Responsive to the phase-frequency difference signal, the current flow control circuit controls flow-in and flow-out of current supplied therefrom/to produce a current flow control signal. The current flow control signal indicates the flow-out of the current when the phase-frequency difference signal indicates the lag phase. The current flow control signal indicates the flow-in of the current when the phase-frequency difference signal indicates the lead phase. Supplied with the current flow control signal, the loop filter filters the current flow control signal into a filtered signal as the control voltage signal. More particularly, the loop filter comprises a filter capacitor which is selectively charged and discharged when the current flow control signal indicates the flow-out and the flow-in of the current, respectively.
In a conventional PLL frequency synthesizer, changing of the output frequency is carried out by changing step by step the designated dividing number D. Therefore, the PLL frequency synthesizer has a variable delay amount on changing the output frequency. As a result, a frequency error of the output frequency occurs in the PLL frequency synthesizer on changing the output frequency. Accordingly, the conventional PLL frequency synthesizer is defective in that it is impossible to change the output frequency at a high speed.